1. Field of the Invention
The present invention relates to circuits used for equalizing propagation delays of signals in a circuit. In particular, the invention relates to the use of delay-locked loops to equalize propagation delays.
2. Description of the Related Art
A data switch may be implemented with a number of channels for transmitting data. The channels may be grouped into a number of parts. However, variations in the fabrication process, operating voltages, and operating temperature of the various parts can undesirably increase signal skew between channels. This problem increases with the number of parts.
In other instances it is desirable to limit the number of channels implemented on each part. For example, for the DP83890 Private Data Exchange (PDX) from National Semiconductor Corp., Santa Clara, Calif. it was desired to integrate no more than 9 channels on a single part. (For example, eight channels for data and one channel for a clock signal.) A solution was needed to ensure that propagation delays through any N parts on printed circuit board would be substantially equal, to minimize skew between channels (e.g., 24 channels on three parts for the PDX). Otherwise there is no sampling eye at the receiver when a printed circuit board has both a fast part and a slow part on it.
The present invention addresses these and other problems of the prior art by providing an apparatus for and method of equalizing propagation delay.
According to one embodiment, an apparatus according to the present invention includes a circuit for generating a signal for equalizing propagation delay among parts of a transceiver. The parts each having a plurality of channels, with each channel being configured to receive the signal. The apparatus comprises a master circuit and a dummy channel circuit. The master circuit is configured to receive and lock to a reference clock signal and in accordance therewith generate a reference delay signal and an adjusted clock signal. The dummy channel circuit is configured to receive the adjusted clock signal, the reference delay signal and a dummy data signal, and in accordance therewith generate an intermediate data signal, the dummy data signal and one or more control signals. The one or more control signals correspond to a delay between the adjusted clock signal and the intermediate data signal.
According to another embodiment, a method according to the present invention equalizes propagation delay among parts of a transceiver. The parts each have a plurality of channels, with each channel being configured to receive a signal for setting a delay period. The method includes the steps of receiving and locking to a reference clock signal; and generating a reference delay signal and an adjusted clock signal, in accordance with the step of receiving and locking. The method further includes the step of receiving the adjusted clock signal, the reference delay signal and a dummy data signal. The method still further includes the step of generating an intermediate data signal, the dummy data signal and one or more control signals, in accordance with the step of receiving the adjusted clock signal, wherein the one or more control signals correspond to a delay between the adjusted clock signal and the intermediate data signal.
A better understanding of the features and advantages of the present invention will be obtained by reference to the following detailed description and accompanying drawings which set forth illustrative embodiments in which the principles of the invention are utilized.